An Embedded Decryption/Decompression Engine using HandelC
Farnaz Gharibian, Kenneth B. Kent
Faculty of Computer Science, University of New Brunswick, Canada
Introduction
1
DecRO
2
• Speed and security of data streams are two key factors in different areas such as data
communication and multimedia.
• The high level architectural view of the decryption/decompression (DecRO) engine
is shown in the figure below.
• Compression algorithms are applied to data streams to increase their
communication speed.
•The engine is comprised of the AES component (decryption), LZ77 component
(decompression) and two buffers.
• Encryption algorithms are used for assuring the security of the data.
• We propose a model to implement both algorithms, decryption and decompression,
in a Field Programmable gate Array chip using HandelC.
AES
Data In
B
u
f
f
e
r
B
u
f
f
e
r
LZ77
Data Out
FPGA
AES
3
LZ77
• Pipelining is used in the design of each round of the AES algorithm as shown in the
figure below.
Encrypted
Data
B
u
f
f
e
r
Round
...
Round
B
u
f
f
e
r
4
• Pipelining is used in the design of LZ77 algorithm as shown in the figure below.
Decrypted
Data
Round
a) Round Loop Architecture
Read Phrase
InvMixColumn
addRoundKey
InvByteSub
InvShiftRow
InvMixColumn
Find Substring
Shift
Read Phrase
Compare
Find Substring
Shift
Read Phrase
Compare
addRoundKey
addRoundKey
InvShiftRow
InvByteSub
InvMixColumn
InvShiftRow
InvByteSub
Compare
Find Substring
Shift
b) The components in each Round
Implementation
5
• The figure below shows the final implementation design of the DecRO engine.
Pipelining and parallelism is used in our implementation.
AES
Data In
FIFO
Channel
• Table below shown throughput results for three different implementation.
• Table below shows Throughput, Maximum Frequency and Resource usage for the
final implementation.
Read
Inv-Sub
Compare
Process
Out
Read
Compare
Process
Out
Read
Compare
Process
Out
Read
Compare
Process
RAM
Round Loop
6
Data Out
LZ77
Initial Round
Add-Key
Inv-Mul
RAM
Final Round
Simulation Results
Out